1. Field of the Invention
The present invention relates to amplitude conversion circuits. In particular, the present invention relates to an amplitude conversion circuit for changing an amplitude of a signal.
2. Description of the Background Art
FIG. 27 is a block diagram showing a configuration of a part of a conventional cellular phone that is involved in image display.
Referring to FIG. 27, the cellular phone includes a control LSI 71 which is a MOST (MOS transistor) integrated circuit, a level shifter 72 which is also a MOST integrated circuit, and a liquid crystal display 73 which is a TFT (thin-film transistor) integrated circuit.
Control LSI 71 generates a control signal for liquid crystal display 73. The control signal has an H or logical high level of 3 V and an L or logical low level of 0 V. Although a large number of control signals are actually generated, it is herein assumed, for convenience of description, that one control signal is generated. Level shifter 72 converts the logic level of the control signal supplied from control LSI 71 to generate an internal control signal. The internal control signal has an H level of 7.5 V and an L level of 0 V. Liquid crystal display 73 presents an image according to the internal control signal from level shifter 72.
FIG. 28 is a circuit diagram showing a configuration of level shifter 72. Referring to FIG. 28, level shifter 72 includes P-channel MOS transistors 74 and 75 and N-channel MOS transistors 76 and 77. P-channel MOS transistors 74 and 75 are connected between a node N71 of a power supply potential VCC (7.5 V) and output nodes N74 and N75 respectively, and have respective gates connected to output nodes N75 and N74 respectively. N-channel MOS transistors 76 and 77 are connected respectively between output nodes N74 and N75 and a node of a ground potential GND, and have respective gates receiving input signals VI and /VI.
Here, it is supposed that input signals VI and /VI respectively have L level (0 V) and H level (3 V) while output signals VO and /VO respectively have H level (7.5 V) and L level (0 V). Then, MOS transistors 74 and 77 are turned on while MOS transistors 75 and 76 are turned off.
In this state, input signal VI is raised from L level (0 V) to H level (3 V) and input signal /VI is lowered from H level (3 V) to L level (0 V). Then, N-channel MOS transistor 76 is turned on first to cause the potential on output node N74 to decrease. When the potential on output node N74 decreases below the potential determined by subtracting the absolute value of a threshold voltage of P-channel MOS transistor 75 from power supply potential VCC, P-channel MOS transistor 75 is turned on to start increase of the potential on output node N75. The increasing potential on output node N75 decreases the source-gate voltage of P-channel MOS transistor 74 and accordingly increases the ON resistance value of P-channel MOS transistor 74, and the potential on output node N74 further decreases. The circuit thus operates in positive feedback manner so that output signals VO and /VO have L level (0 V) and H level (7.5 V) respectively and the level converting operation is completed.
A level shifter disclosed for example in Japanese Patent Laying-Open No. 11-145821 has P-channel MOS transistors 74 and 75 with respective gates both connected to one output node N74 or N75.
As discussed above, the conventional level shifter 72 operates on the precondition that N-channel MOS transistor 76 is turned on in response to rising of input signal VI from L level (0 V) to H level (3 V). In order to render N-channel MOS transistor 76 conductive, the threshold voltage of N-channel MOS transistor 76 must be H level (3 V) or less of input signal VI.
The threshold voltage of a commonly used semiconductor LSI is easily set at 3V or less. However, there is a considerable difference in the threshold voltage between low-temperature polysilicon TFTs included in the liquid crystal display, which makes it difficult to set the threshold voltage of the TFTs at 3 V or less. Then, as shown in FIG. 27, level shifter 72 constituted of high-withstand-voltage MOS transistors is provided between control LSI 71 and liquid crystal display 73 to change the logic level of the signal.
However, the cost of level shifter 72 thus provided adds to the system cost, resulting in increase of the system cost.